High-level estimation and exploration of reliability for multi-processor system-on-chip 1st ed.

Author

• Wang, Zheng

Additional Author(s)

• Chattopadhyay, Anupam

Publisher

Singapore: Springer Nature Singapore Pte Ltd., 2018

Language

English

ISBN

9789811010736

Series

Computer architecture and design methodologies

Subject(s)

• FAULT-TOLERANT COMPUTING
• SYSTEMS ON A CHIP
• COMPUTER SOFTWARE--REUSABILITY

Notes

. .

Abstract

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .

Physical Dimension

Number of Page(s)

1 online resource (xx, 197 p.)

Dimension

-

Other Desc.

ill. (in color.)

Summary / Review / Table of Content

Introduction --
Background --
Related Work --
High-level Fault Injection and Simulation --
Architectural Reliability Estimation --
Architectural Reliability Exploration --
System-level Reliability Exploration --
Conclusion and Outlook.

Exemplar(s)

#	Accession No.	Call Number	Location	Status
1.	01363/20	006.22 Wan H	Online !	Available